ADC1 Register Reference Chapter

1 General description

ADC1 converts an analog input voltage into a 12-bit digital result. The ADC path is GPIO analog input -> ADC_SQR3-selected Analog MUX -> Sample & Hold -> ADC converter -> ADC_DR, with status and transfer helpers such as EOC, DMA, and Analog watchdog around that path.

A GPIO pin is the physical analog pad, while the ADC channel number is the selector value that tells the regular sequencer and Analog MUX which input to forward. For example, PA1 maps to ADC1_IN1, while other package pins map to different ADC channel numbers. The channel selection logic controls the MUX; it is not another signal-processing stage after it.

In the current motor-driver trainer lab, PA1 carries the CURRENT_SENSE signal. That fixed implemented route is separate from full STM32-style multiplexed channel coverage.

2 Main features

3 Reference figures and tables

Figure 1. Reconstructed ADC regular-conversion path based on RM0008 Figure 22

Reference source: RM0008 Reference Manual, p.217, Figure 22. Single ADC block diagram.

What this figure means: This redraw follows the RM0008 Figure 22 reading direction but isolates the regular-conversion path used in this chapter. Injected conversion blocks, ADC3-only trigger variants, and remap branches are intentionally left out of the figure so the main path GPIO analog pad -> ADC_SQR3-controlled Analog MUX -> Sample & Hold -> converter -> ADC_DR stays clear. ADC_SQR3.SQ1 controls which MUX input is forwarded; it is not a serial signal-processing block after the MUX.

Related registers: ADC_SQRx, ADC_SMPRx, ADC_CR2, ADC_SR, ADC_DR.

Figure 2. Reconstructed ADC input equivalent circuit based on DS5319 Figure 38

Reference source: STM32F103 Datasheet, p.77, Figure 38. Typical connection diagram using the ADC.

What this figure means: This redraw follows the official equivalent-circuit layout. The ADC does not read the input wire directly forever. It must briefly charge an internal sampling capacitor, so source impedance and sample time directly affect accuracy.

Related registers: ADC_SMPR1, ADC_SMPR2.

Figure 3. Reconstructed regular conversion timing based on RM0008 Figure 23

Reference source: RM0008 Reference Manual, p.220, Figure 23. Timing diagram.

What this figure means: This redraw follows the original timing-lane layout. Enabling the ADC does not instantly produce a valid result. After enable and trigger, the converter spends time sampling and converting, then ADC_SR.EOC indicates completion and ADC_DR becomes readable.

Related registers: ADC_CR2.ADON, ADC_CR2.SWSTART, ADC_SR.EOC, ADC_DR.

Figure 4. Reconstructed analog watchdog guarded area based on RM0008 Figure 24

Reference source: RM0008 Reference Manual, p.220, Figure 24. Analog watchdog guarded area.

What this figure means: This redraw follows the official guarded-area layout. The analog watchdog compares each conversion result with configured high and low thresholds. If a result leaves the allowed range, the watchdog sets the status flag.

Related registers: ADC_HTR, ADC_LTR, ADC_CR1.AWDEN, ADC_SR.AWD.

Reference source: STM32F103 Datasheet, p.29, Table 5. Pin definitions. What this table means: GPIO pin names and ADC channel numbers are different concepts. Related registers: ADC_SQRx, GPIOx_CRL, GPIOx_CRH; for the current trainer route, PA1 means GPIOA_CRL[7:4] plus ADC1_IN1.

3.1 PA1 and PA6 GPIO nibbles before ADC conversion

Write the field as GPIOA->CRL &= ~(0xFu << 4). The complete 0x0..0xF mode table and shift calculation are in the GPIO Register Datasheet.

4 Official ADC1 register map

The register block below follows RM0008 Rev 21, Section 11.12 and Table 72. ADC peripheral registers are accessed as 32-bit words. Absolute addresses use ADC1 base 0x40012400 + offset.

Source: RM0008 Rev 21, Section 11.12, Table 72. The table keeps the complete official map visible even when a register is not executable in the trainer.

5 Register descriptions

Yellow fields have an active trainer side effect. Blue fields are official fields that remain stored or are shown for register reading. Reserved fields must remain at their reset value.

5.1 ADC status register (ADC_SR)

Address offset: 0x00   Address: 0x40012400   Reset value: 0x00000000

5.2 ADC control register 1 (ADC_CR1)

Address offset: 0x04   Address: 0x40012404   Reset value: 0x00000000

5.3 ADC control register 2 (ADC_CR2)

Address offset: 0x08   Address: 0x40012408   Reset value: 0x00000000

Shared ADC_CR2 EXTSEL decoder: the values below are official RM0008 regular-group trigger selections. The trainer execution column is a separate support boundary.

5.4 ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x10   Address: 0x40012410   Reset value: 0x00000000

5.5 ADC regular sequence register 3 (ADC_SQR3)

Address offset: 0x34   Address: 0x40012434   Reset value: 0x00000000

5.6 ADC regular data register (ADC_DR)

Address offset: 0x4C   Address: 0x4001244C   Reset value: 0x00000000

5.7 Reference-only ADC register field details

These official registers stay in the ADC1 map so students can recognize the complete RM0008 block. They are not exposed as focused trainer fields unless the trainer behavior column says otherwise.

6 Trainer contract and legacy boundary

The register-value behavior above is enough to review ADC code. The companion ADC User Description owns learner-facing UI confirmation steps; the same pasteable core sequence is included at the end of this chapter. Student C uses the sandbox pointer ADC1 = 0x1200, whose exposed field offsets mirror the official register layout above.

Legacy compatibility only: ADC1_CR = 0x50001000, ADC1_DR_CH0 = 0x50001004, and ADC1_DR_CH1 = 0x50001008. These private Trainer aliases are not part of the official ADC1 map and are not used by the active P02 ADC code.

Reference-only on real STM32F103: injected conversions, DMA execution, analog watchdog execution, TIM3/TIM4 trigger runtime, calibration timing, continuous/scan sequencing, and cycle-accurate ADCCLK timing.

6.1 Current trainer code example

현재 기본 실행 기준: PA1/ADC1_IN1, PA6/ADC1_IN6, PB0/ADC1_IN8을 SQ1 → SWSTART → EOC polling → ADC_DR 순서로 순환 측정합니다. 이 실행 예제는 private ADC alias나 interrupt handler를 사용하지 않으며, sample cycle 효과가 모델링되지 않은 ADC_SMPR2 설정도 넣지 않습니다.

volatile uint32_t current_raw = 0u;
volatile uint32_t angle_raw = 0u;
volatile uint32_t ntc_raw = 0u;
volatile uint32_t adc_channel = 6u;

static void adc_start(uint32_t channel)
{
    ADC1->SQR3 = channel;               /* 다음에 변환할 ADC 채널을 선택합니다. */
    ADC1->CR2 |= ADC_CR2_SWSTART;       /* 선택한 채널의 변환을 실제로 한 번 시작합니다. */
}

void user_init(void)
{
    trainer_clock_init_72mhz();
    RCC->APB2ENR = RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_ADC1EN;
    RCC->APB1ENR = RCC_APB1ENR_TIM2EN;
    GPIOA->CRL = 0x40422B00u;
    GPIOB->CRL = 0x44444440u;
    ADC1->CR1 = 0u;                          /* EOC polling이므로 interrupt를 끕니다. */
    ADC1->CR2 = ADC_CR2_ADON;                /* ADC를 켭니다. */
    ADC1->CR2 |= ADC_CR2_EXTSEL_SWSTART;     /* regular conversion 시작 방식으로 SWSTART를 선택합니다. */
    ADC1->CR2 |= ADC_CR2_EXTTRIG;            /* 선택한 시작 방식을 허용합니다. 주기 설정이 아닙니다. */
    adc_start(ADC_SQR3_SQ1_ADC1_IN6);
}

void user_loop(void)
{
    uint32_t raw;
    if ((ADC1->SR & ADC_SR_EOC) == 0u) return;
    raw = ADC1->DR;
    if (adc_channel == 6u) {
        angle_raw = raw;
        adc_channel = 8u;
        adc_start(ADC_SQR3_SQ1_ADC1_IN8);
    } else if (adc_channel == 8u) {
        ntc_raw = raw;
        adc_channel = 1u;
        adc_start(ADC_SQR3_SQ1_ADC1_IN1);
    } else {
        current_raw = raw;
        adc_channel = 6u;
        adc_start(ADC_SQR3_SQ1_ADC1_IN6);
    }
    watch_u32("angle_raw", angle_raw);
    watch_u32("ntc_raw", ntc_raw);
    watch_u32("current_raw", current_raw);
}