EXTI Datasheet

1 General description

The external interrupt / event controller generates interrupt requests from selected GPIO input transitions. Each EXTI line may be masked or unmasked, and rising edge or falling edge detection can be enabled independently. When a configured edge is detected, the corresponding pending bit is set until cleared by software.

In the implemented subset used by the site, line 6 is the primary line of interest. On the real STM32F103, EXTI line 6 can be sourced from PA6, PB6, PC6, and the matching line-6 pad on other ports through AFIO_EXTICR2. The current trainer keeps only the fixed PA6 -> EXTI6 -> HALL_IN route.

Figure 1. Official EXTI6 source-selection concept and the current fixed PA6 trainer route

Source reconstruction from RM0008 Rev 21 Figure 21, External interrupt/event GPIO mapping, and AFIO_EXTICR2 register description, with DS5319 Rev 20 pin-table context. Reconstructed trainer-scope drawing; no vendor PDF image was pasted.

2 Main features

• Maskable interrupt line
• Independent rising and falling edge trigger definition in the official register model
• Sticky pending flag cleared by write-1
• GPIO input and EXTI configuration separated into different register groups

3 EXTI architecture

Figure 2. EXTI6 internal block flow reconstructed from the STM32F103 reference-manual model

Source reconstruction from RM0008 Rev 21 Figure 20, External interrupt/event controller block diagram, and EXTI register descriptions for IMR, EMR, RTSR, FTSR, SWIER, and PR. Trainer scope is PA6/HALL_IN rising-edge handling.

The trainer-relevant path is Hall sensor to PA6 to EXTI6 to pending flag to ISR. Falling-edge configuration remains exposed for reference-manual shape, but the current lab flow uses rising Hall pulses only. Event mode and software interrupt injection are official RM0008 reference paths; the current trainer header/MMIO map does not expose EXTI_EMR or EXTI_SWIER as executable registers.

4 Register map and reset values

The offsets in this table are the official RM0008 EXTI offsets. The trainer's C pointer struct is compacted to the exposed subset, while the symbolic constants EXTI_IMR, EXTI_RTSR, EXTI_FTSR, and EXTI_PR preserve the official addresses for read_reg() / write_reg() examples.

5 Register descriptions

6 Student register guide and code examples

• Read the current path as RCC gate -> PA6 input mode -> EXTI rising edge -> pending bit -> ISR clear.
• RCC->APB2ENR does not connect directly to a pin. It first powers the AFIO/GPIOA register path, and that path later changes what the UI can observe.
• The current trainer keeps PA6 -> EXTI6 -> HALL_IN fixed, so the interrupt flow stays visible before full source remapping is introduced.

6.1 Current trainer code example

// Current trainer: PA6 -> EXTI6 -> HALL_IN route is fixed
RCC->APB2ENR |= (1u << 0);   // AFIOEN
RCC->APB2ENR |= (1u << 2);   // IOPAEN

GPIOA->CRL &= ~(0xFu << (6 * 4));
GPIOA->CRL |=  (0x4u << (6 * 4));  // PA6 input for Hall signal

EXTI->IMR  |= (1u << 6);
EXTI->RTSR |= (1u << 6);
EXTI->FTSR &= ~(1u << 6);

void EXTI6_IRQHandler(void)
{
    if ((EXTI->PR & (1u << 6)) != 0) {
        EXTI->PR = (1u << 6);  // clear pending
    }
}

Watch this code in Register View RCC_APB2ENR, GPIOA_CRL, EXTI_IMR, EXTI_RTSR, and EXTI_PR, then confirm the same Hall signal in Pin View and Graph View.

6.2 Full STM32F103 reference notes

On the real STM32F103, line 6 source selection is programmed through AFIO_EXTICR2.EXTI6[3:0]; value 0000 selects PA6. Official firmware services line 6 through the shared EXTI9_5_IRQHandler vector.

Those official names are intentionally kept as reference text, not trainer code. The current trainer exposes the fixed PA6 -> EXTI6 -> HALL_IN route and the dedicated EXTI6_IRQHandler hook because only the Hall route is modeled.