EXTI Datasheet

1 General description

The external interrupt / event controller generates interrupt requests or event pulses from selected GPIO input transitions. Each EXTI line may be masked or unmasked, and rising edge or falling edge detection can be enabled independently. When a configured trigger reaches an interrupt branch that is unmasked in EXTI_IMR, the corresponding pending bit is set until cleared by software. An event-only branch enabled through EXTI_EMR produces an event pulse without setting EXTI_PR.

In the implemented subset used by the site, line 6 is the primary line of interest. On the real STM32F103, EXTI line 6 can be sourced from PA6, PB6, PC6, and the matching line-6 pad on other ports through AFIO_EXTICR2. The current trainer keeps only the fixed PA6 -> EXTI6 -> HALL_IN route.

Figure 1. Official EXTI6 source-selection concept and the current fixed PA6 trainer route

Source reconstruction from RM0008 Rev 21 Figure 21, External interrupt/event GPIO mapping, and AFIO_EXTICR2 register description, with DS5319 Rev 20 pin-table context. Reconstructed trainer-scope drawing; no vendor PDF image was pasted.

2 Main features

• Maskable interrupt line
• Independent rising and falling edge trigger definition in the official register model
• Sticky pending flag cleared by write-1
• GPIO input and EXTI configuration separated into different register groups

3 EXTI architecture

Figure 2. EXTI interrupt/event controller architecture reconstructed from the STM32F103 reference-manual model

Direct raster reconstruction from RM0008 Rev 21 Figure 20, External interrupt/event controller block diagram, and the EXTI register descriptions for IMR, EMR, RTSR, FTSR, SWIER, and PR. This is not a pasted vendor PDF crop. The interrupt branch shown here is trigger request -> IMR gate -> PR pending latch -> handler, and a write-1 to PRx clears the latched request. The event branch uses EMR and the pulse generator without passing through PR. Trainer scope is PA6/HALL_IN rising-edge handling.

Read Figure 2 as Input Line -> edge detect / SWIER request -> interrupt and event branches. A selected edge creates one request for the transition; holding the input HIGH does not create repeated requests. The trainer-relevant interrupt path is Hall sensor to PA6 to EXTI6 to the IMR.MR6 interrupt gate to the PR.PR6 pending latch to ISR. In the official event path, the edge/software-trigger result branches through EMR.MR6 and the pulse generator without passing through either IMR or the pending latch. The event pulse does not feed back into PR. If event and interrupt branches are both enabled, the same trigger sets PR through the independently enabled IMR branch, not through the event pulse. Falling-edge configuration remains exposed for reference-manual shape, but the current lab flow uses rising Hall pulses only. Event mode and software interrupt injection are official RM0008 reference paths; the current trainer header/MMIO map does not expose EXTI_EMR or EXTI_SWIER as executable registers.

Figure 20 uses /19 to mark 19 parallel lanes, EXTI0 through EXTI18. Connectivity-line devices add Ethernet-wakeup EXTI19; bit 19 is reserved on other devices. CPU register accesses travel through the AMBA APB bus and the EXTI peripheral interface, which is clocked by PCLK2, but RCC has no separate EXTIEN bit. AFIOEN is required to program AFIO_EXTICRx, and the owning GPIO port clock is required to configure the GPIO input path.

GPIO EXTI mapping follows the pin index: Px0 maps to EXTI0 through Px15 maps to EXTI15. For each EXTI line, AFIO_EXTICRx selects exactly one available port source at a time; EXTI6 cannot receive PA6, PB6 and PC6 simultaneously. The current trainer fixes that selection to PA6 / HALL_IN.

3.1 PA6 GPIO nibble before EXTI6

The field write is GPIOA->CRL = (GPIOA->CRL & ~(0xFu << 24)) | (0x4u << 24). See the GPIO Register Datasheet for the complete nibble table.

DS5319 Rev 20 does not mark PA6 as an FT (5 V-tolerant) pin, and its absolute-maximum table limits an input on any other pin to 4.0 V. The Trainer's Board and Graph 0/5 V Hall display is virtual proof only. Do not connect a real 5 V Hall output directly to STM32F103C8 PA6; use suitable level conditioning.

4 Register map and reset values

RM0008 contains a reset-notation discrepancy for EXTI_PR: Table 64 lists PR[19:0] as zero in the register map, while Section 10.3.6 labels the detailed register reset value Undefined. The map row above preserves Table 64; the detailed description below preserves Section 10.3.6. Software should clear any handled pending bit with write-1-to-clear rather than relying on an assumed initial PR value. This official discrepancy is separate from the current trainer: the trainer deterministically initializes EXTI_PR to 0x00000000 on reset.

RM0008 requires every EXTI peripheral register to be accessed as a 32-bit word. Across all six registers (EXTI_IMR, EXTI_EMR, EXTI_RTSR, EXTI_FTSR, EXTI_SWIER, and EXTI_PR), bit 19 is implemented on connectivity-line devices only and is reserved on the other STM32F103 device groups.

The offsets in this table are the official RM0008 EXTI offsets. The trainer's C pointer struct preserves those offsets: unsupported EXTI_EMR and EXTI_SWIER slots are reserved at 0x04 and 0x10, so EXTI->RTSR, EXTI->FTSR, and EXTI->PR stay aligned with the official layout. Symbolic constants preserve the same official addresses for read_reg() / write_reg() examples.

5 Register descriptions

6 Student register guide and code examples

• Read the current path as RCC gate -> PA6 input mode -> EXTI rising edge -> pending bit -> ISR clear.
• RCC->APB2ENR does not connect directly to a pin. It first powers the AFIO/GPIOA register path, and that path later changes what the UI can observe.
• The current trainer keeps PA6 -> EXTI6 -> HALL_IN fixed, so the interrupt flow stays visible before full source remapping is introduced.

6.1 Current trainer code example

volatile uint32_t hall_irq_count = 0u;
volatile uint32_t exti_pr_before_clear = 0u;

void user_init(void)
{
    /* Current trainer: PA6 -> EXTI6 -> HALL_IN route is fixed. */
    trainer_clock_init_72mhz();
    RCC->APB2ENR = RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPAEN;
    RCC->APB1ENR = RCC_APB1ENR_TIM2EN;

    /* PA2 PWM, PA3 driver enable, PA4 direction, PA6 Hall input. */
    GPIOA->CRL = 0x44422200u;
    TIM2->PSC = 11999u;
    TIM2->ARR = 99u;
    TIM2->CCR1 = 70u;
    TIM2->CCER = TIM2_CCER_CC1E;
    TIM2->CR1 = TIM2_CR1_CEN;
    GPIOA->BSRR = GPIOA_DRV_EN_BIT;

    EXTI->IMR = EXTI_IMR_MR6;
    EXTI->RTSR = EXTI_RTSR_TR6;
    EXTI->FTSR = 0u;
    EXTI->PR = EXTI_PR_PR6;
}

void user_loop(void)
{
    watch_u32("HALL_COUNT", HALL->COUNT);
    watch_u32("hall_irq_count", hall_irq_count);
    watch_u32("exti_pr_before_clear", exti_pr_before_clear);
}

void EXTI6_IRQHandler(void)
{
    if ((EXTI->PR & EXTI_PR_PR6) != 0u) {
        exti_pr_before_clear = EXTI->PR;
        hall_irq_count++;
        EXTI->PR = EXTI_PR_PR6;  /* write 1 to clear */
    }
}

This example deliberately starts TIM2 PWM and PA3 driver enable because EXTI configuration alone cannot create a Hall edge. Watch this code in Registers through RCC_APB2ENR, GPIOA_CRL, EXTI_IMR, EXTI_RTSR, and EXTI_PR. Then select PA6 / HALL_IN in Board Lab pin routes, compare Official device functions with Current trainer route, and confirm the automatically added pulse trace in Graph. The companion EXTI6/Hall User Description maps every step and boundary.

6.2 Full STM32F103 reference notes

On the real STM32F103, line 6 source selection is programmed through AFIO_EXTICR2[11:8] (EXTI6[3:0]); value 0000 selects PA6. Official firmware services line 6 through the shared EXTI9_5_IRQHandler vector.

Those official names are intentionally kept as reference text, not trainer code. The current trainer exposes the fixed PA6 -> EXTI6 -> HALL_IN route and the dedicated EXTI6_IRQHandler hook because only the Hall route is modeled.