GPIO Register Datasheet

1 General description

GPIOA is a 16-bit general-purpose I/O port. Each port bit can be programmed independently as a digital input, digital output, alternate-function output, or analog input, depending on the selected mode and configuration bits. The port provides separate input and output data paths, atomic bit set/reset access, and configuration lock capability.

GPIOA configuration is controlled through the low and high configuration registers (GPIOA_CRL and GPIOA_CRH). Runtime data access is performed through GPIOA_IDR, GPIOA_ODR, GPIOA_BSRR, GPIOA_BRR reset-only compatibility register, and GPIOA_LCKR.

In the real STM32F103 clock tree, the GPIOA register block sits on the APB2 bus. That means the GPIO chapter should always be read together with RCC->APB2ENR.IOPAEN: without the port clock, CRL/CRH configuration and pad-level I/O behavior are not part of an active peripheral path.

These are GPIO usage examples, not a complete product firmware pattern. Real products map LEDs, driver-enable lines, Hall signals, buttons, and communication pins according to their board schematic.

See the separate RCC Clock Control Datasheet for peripheral clock-enable details. For PA1 / CURRENT_SENSE, GPIO analog mode is only the pad-side prerequisite; RCC->APB2ENR.ADC1EN opens the ADC register path. The PA1 / CURRENT_SENSE analog flow continues in the separate ADC1 Datasheet as IOPAEN -> ADC1EN -> ADCCLK -> analog mode -> conversion.

2 Main features

• GPIOA register block sits on the APB2 bus and requires RCC->APB2ENR.IOPAEN.
• Each pin uses a 4-bit CNFy/MODEy nibble in GPIOA_CRL or GPIOA_CRH.
• IDRy reads the input path; ODRy provides the output latch value.
• BSRR and BRR update output latches atomically.

3 GPIO port architecture

GPIO figures show the input buffer, output driver, alternate-function path, and analog high-impedance path; they are not trainer-board wiring diagrams.

Figure 1. GPIO port-bit architecture

Source reconstruction from RM0008 Rev 21 GPIO port-bit architecture figures; no vendor PDF image was pasted.

Figure 2. GPIO input configuration

Source reconstruction from RM0008 Rev 21 input configuration figure and GPIO mode table.

Figure 3. GPIO output configuration

Source reconstruction from RM0008 Rev 21 output configuration figure and bit set/reset model.

Figure 4. GPIO alternate-function configuration

Source reconstruction from RM0008 Rev 21 alternate-function output configuration figure.

Figure 5. GPIO analog configuration

Source reconstruction from RM0008 Rev 21 analog input configuration figure and ADC pad-mode notes.

Figure 6. STM32F103C8 GPIOA package pinout reference

Reference source: STM32F103C8 MCU datasheet package pinout, redrawn for the local GPIOA chapter.

3.1 How to read Figures 2-5

4 I/O port bit configuration

Each pin field is [CNF1 CNF0 MODE1 MODE0]. Section 4.1 tells where the 4-bit field sits inside CRL/CRH; Section 4.2 decodes the value written there into actual STM32F103 pin behavior. The complete configuration truth appears once in Section 4.2.

4.1 Register field placement and pin-number lookup

Read a pin name as Pxy: x selects the port register block and y is the pin number. Thus PA0 uses GPIOA fields with suffix 0, while PB3 uses GPIOB fields with suffix 3. RM0008 defines x=A..G; the current Trainer exposes GPIOA and GPIOB.

Worked lookups: PA0 mode is GPIOA_CRL[3:0], split into CNF0[3:2] and MODE0[1:0]. Its input/output data bit is bit 0; its BSRR set bit is 0, BSRR reset bit is 16, and BRR reset bit is 0. For PA3, x=A, y=3 -> GPIOA_CRL[15:12].

To program a mode without changing neighboring pins, first choose shift = 4*y for CRL or shift = 4*(y-8) for CRH, clear only 0xF << shift, then insert the Section 4.2 nibble at that shift. For example, 0x2 means CNF=00, MODE=10: general-purpose push-pull output, maximum 2 MHz.

4.2 Combined 4-bit nibble value to actual pin behavior

5 Package pinout and pin definitions

5.1 Datasheet-style pin definition excerpt

6 Register map and reset values

The port letter selects the base address; every port then uses the same register offsets shown below.

The offset table uses GPIOA names for concrete addresses. Replace GPIOA with GPIOB to address the same fields in the GPIOB block.

7 Register descriptions

For GPIOA_CRL and GPIOA_CRH, use Section 4.1 to locate each 4-bit field and Section 4.2 to decode the written nibble. Current trainer routes and their visible board results remain in Section 8.6.

8 Student register guide and code examples

8.1 Quick first practice path

8.2 Input configuration sequence

Set MODEy = 00; use 0x4 for floating input or 0x8 for pull-up/down. PA5 is the local GPIO input route PA5 / FAULT_IN.

8.3 Output configuration sequence

Enable IOPAEN, write GPIOA_CRL[15:12] for PA3, then write ODR3, BS3, or BR3. If the setup is wrong, the trainer may show output writes latch only, GPIOA clock gated / 0.00 V, or Pin mode is not output / 0.00 V.

8.4 Practical notes

The current System Trainer named routes are PA10 / UART_RX, PB0 / TEMPERATURE_SENSE, PA1 / CURRENT_SENSE, PA2 / PWM_OUT, PA3 / DRV_EN, PA4 / DRV_DIR, PA5 / FAULT_IN, and selectable PA6 / FEEDBACK_IN.

• Alternate-function outputs still require a correct GPIO nibble and peripheral clock.
• PB0 NTC ADC and PA10 UART are electrically and logically independent inputs.
• HALL uses a 3.3 V open-collector pull-up and executable AFIO_EXTICR2.EXTI6=0000; ANGLE uses AS5600 analog OUT with the local OUTS=00 / MANG=180° profile.
• Vendor sensor tolerances, AS5600 programming/diagnostics, and automatic motor-driver protections are reference-only unless a specific Trainer proof is listed.

8.5 Current trainer code examples

These examples keep the System Trainer mode map and use GPIOA_ODR only for PA3/PA4 output changes. RCC_APB2ENR opens the port register path, GPIOx_CRL selects each four-bit pin mode, and ODR bits 3 and 4 directly control the modeled Enable and Direction latches. BSRR/BRR remain part of the official register reference above but are intentionally excluded from this minimum executable path. As official electrical reference truth, PB1 open-drain drives LOW when ODR1=0 and is released when ODR1=1; PB1 is reference-only and is not part of the executable System harness.

GPIOA ODR minimum example: configures the common PA1~PA6 routes and changes only PA3 Enable and PA4 Direction through ODR.

volatile uint32_t gpio_stage = 0u;

void user_init(void)
{
    trainer_clock_init_72mhz();
    RCC->APB2ENR = RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_ADC1EN | RCC_APB2ENR_USART1EN;
    RCC->APB1ENR = RCC_APB1ENR_TIM2EN;
    GPIOA->CRL = 0x44422B00u;
    GPIOB->CRL &= ~0xFu; /* PB0 / ADC1_IN8 NTC divider node */
    if (TRAINER->FEEDBACK_MODE == TRAINER_FEEDBACK_ANGLE) {
        GPIOA->CRL &= ~(0xFu << 24);
    } else {
        AFIO->EXTICR[1] &= ~(0xFu << 8); /* EXTI6 = Port A / PA6 */
    }
    GPIOA->ODR &= ~(GPIOA_DRV_EN_BIT | GPIOA_DRV_DIR_BIT);

    watch_u32("gpio_stage", gpio_stage);
    watch_u32("GPIOA_CRL", GPIOA->CRL);
    watch_u32("GPIOA_ODR", GPIOA->ODR);
}

void user_loop(void)
{
    switch (gpio_stage)
    {
        case 0:
            GPIOA->ODR |= GPIOA_DRV_EN_BIT;
            break;
        case 1:
            GPIOA->ODR |= GPIOA_DRV_DIR_BIT;
            break;
        case 2:
            GPIOA->ODR &= ~GPIOA_DRV_EN_BIT;
            break;
        case 3:
            GPIOA->ODR &= ~GPIOA_DRV_DIR_BIT;
            break;
        default:
            break;
    }

    if (gpio_stage < 4u) gpio_stage++;
    watch_u32("gpio_stage", gpio_stage);
    watch_u32("GPIOA_ODR", GPIOA->ODR);
}

8.6 Current System Trainer GPIO connection map

Read each GPIO route in this order: pin-definition evidence first, then the RCC gate, then the GPIO configuration field, then the data register, then the visible board or UI signal. A pin is GPIO-capable in the STM32-style document when its package row is an I/O pad and its main reset function is the same port name, such as PA3 or active NTC input PB0. PB0 is the active NTC ADC route; PB1 remains only to separate official package truth from the current 8-pin System harness.