STM32F103 RCC Clock Control Reference Chapter

Document scope

This chapter follows the official STM32F103 document split: the datasheet provides the big clock-tree view, while RM0008 explains the control registers, prescalers, and peripheral enable sequence. Trainer-executable examples are kept separate in Chapter 9.

1 RCC overview

On STM32F103, RCC performs three jobs. First, it decides which oscillator or PLL output becomes SYSCLK. Second, it divides that system clock into the AHB and APB bus clocks. Third, it enables or disables the bus clock that reaches each peripheral register block.

• HSI, HSE, and PLLCLK are SYSCLK candidates.
• SYSCLK feeds the AHB prescaler to produce HCLK.
• HCLK feeds the APB1 and APB2 prescalers to produce PCLK1 and PCLK2.
• Peripheral registers become readable and writable only after the relevant RCC enable bit is active on real hardware.

2 Clock tree overview

Figure 1. Reconstructed STM32F103 RCC clock-tree slice

Source reconstruction: STM32F103 datasheet (DS5319 Rev 20, Figure 2. Clock tree) and RM0008 Rev 21, Figure 8. Clock tree

The official documents place clock distribution before register details. That order matters because RCC_CR and RCC_CFGR only make sense after the reader can see where SYSCLK, HCLK, PCLK1, PCLK2, and ADCCLK come from.

Figure 1 keeps the clock path uncluttered; exact RCC_CFGR field names and values are listed in Section 6.

• After reset, the internal 8 MHz RC oscillator (HSI) is the default CPU clock.
• AHB and APB2 can run up to 72 MHz.
• APB1 must stay at or below 36 MHz.
• Timer clocks follow the hardware x2 rule whenever the APB prescaler is not 1.

Figure 2. HSE source options: crystal/resonator mode and bypass mode

Source reconstruction: RM0008 Rev 21, Section 7.2.1, Figure 9. HSE/LSE clock sources

3 Derived clocks and important exceptions

4 RCC register map

This complete low-/medium-/high-density STM32F103 RCC block follows RM0008 Rev 21 Section 7.3.11, Table 18. Absolute addresses use RCC base 0x40021000 + offset; official reset values remain separate from trainer reset and side-effect notes.

Official base address: RCC = 0x40021000. Trainer pointer base: RCC = 0x1800. The sandbox block preserves the official offsets above. The focused header exposes CR, CFGR, APB2ENR, and APB1ENR; unsupported positions remain reserved. The sandbox base is not a physical STM32 address.

The three enable registers are expanded separately in Section 7 using the same 32-bit layout and bit-summary format as RCC_CR and RCC_CFGR.

5 Clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83

On a device, RCC_CR is the "turn it on and wait until ready" register. In this trainer, the helper preserves that sequence by writing the ready flags itself; do not interpret a raw HSEON or PLLON write as a simulated oscillator or lock event.

6 Clock configuration register (RCC_CFGR)

Address offset: 0x04
Reset value: 0x00000000

RCC_CFGR is the "which clock do I select and how do I divide it" register. The trainer uses its PLL, HCLK, and PCLK1 fields for TIM2 timing, but does not model PCLK2 or ADCCLK timing. SWS is hardware-owned on STM32; the helper writes it explicitly so its status wait loop has a value to read.

7 AHB/APB enable registers

7.1 AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x14
Reset value: 0x00000014

The official values are stored internally but omitted from the focused Registers list/header because no DMA, SRAM-timing, Flash-interface, or CRC behavior is modeled. GPIO and ADC gates do not belong in this register.

7.2 APB2 peripheral clock enable register (RCC_APB2ENR)

Address offset: 0x18
Reset value: 0x00000000

IOPAEN enables GPIOA for PA2/PA3/PA4, and IOPBEN enables GPIOB for PB0/PB1. Both GPIO port clocks are opened from RCC_APB2ENR; they are not AHB gates.

RM0008 Rev 21 Section 7.3.7 defines bits 31:22 as reserved, bits 21:19 as TIM11EN/TIM10EN/TIM9EN, and bits 18:16 as reserved. Peripheral availability still depends on the selected STM32F103 device. The trainer has no named TIM9/10/11 header macros, decoded rows, timer blocks, or modeled timer effects. A raw write through RCC->APB2ENR can still latch these bits in MMIO and remain visible in the full APB2ENR hex value. Example supported bit write: RCC->APB2ENR |= (1u << 9);

Example whole-register write: RCC->APB2ENR = 0x0000020D

7.3 APB1 peripheral clock enable register (RCC_APB1ENR)

Address offset: 0x1C
Reset value: 0x00000000

Trainer example: RCC->APB1ENR |= (1u << 0); or RCC->APB1ENR = 0x00000001. A real-device-only TIM2EN | TIM3EN value would be 0x00000003.

8 Programming sequences

Official STM32F103 clock-source switching uses RCC_CR, RCC_CFGR, and FLASH_ACR. The current trainer helper uses the same registers for its fixed 72 MHz profile, then student code opens the modeled APB gates directly.

8.1 Current trainer helper: code-to-register review

This is a review of the executable trainer_clock_init_72mhz() helper, not a replacement for the real-device sequence. This chapter must be enough to analyze the helper code by register value; the companion User Description only adds the learner-facing proof route and exception callouts. RM0008 Rev 21 pages 99-103 define the clock-control fields; pages 111-116 define the AHB/APB enable registers. In particular, HSERDY, PLLRDY, and SWS are hardware-owned status fields on a real STM32F103.

9 Student register guide and code examples

9.1 Which RCC registers the student should look at

9.2 Current trainer route and enable examples

An RCC enable opens the peripheral clock and register path; RCC does not select or own the 4-bit GPIO nibble. The actual pin behavior is determined by the matching GPIOx_CRL / GPIOx_CRH field and, when applicable, the peripheral chapter linked below.

9.3 Clock-source checkpoint before trainer gates

Before opening APB peripheral gates, read the clock-source path first: HSI/HSE/PLL -> SYSCLK -> HCLK -> PCLK1/PCLK2. RM0008 describes the HSI reset/default path through RCC_CR.HSION, RCC_CR.HSIRDY, RCC_CFGR.SW, and RCC_CFGR.SWS. The current trainer exposes the real initialization sequence as trainer_clock_init_72mhz() in training_api.h, then lets student code open the modeled APB gates it needs. RCC_AHBENR is not part of the focused student header.

9.4 Current trainer code example

void user_init(void)
{
    // Configure the trainer RCC_CR/RCC_CFGR 72 MHz helper path.
    // HSE 8 MHz -> PLL x9 -> SYSCLK 72 MHz is stored by the helper.
    trainer_clock_init_72mhz();

    // P02 Week 1 gate set: AFIO, GPIOA, GPIOB and ADC1 on APB2.
    RCC->APB2ENR = RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_ADC1EN;

    // TIM2 PWM gate on APB1.
    RCC->APB1ENR = RCC_APB1ENR_TIM2EN;
}

void user_loop(void)
{
}

This is the P02 Week 1 gate set used by the peripheral-specific RCC, GPIO, ADC, TIM2 PWM, and motor-driver examples. USART1 is added separately by the Week 2 RX-only initialization.

9.5 Full STM32F103 register sequence behind the helper

Reference-only on real STM32F103 hardware: use the Section 9.4 helper in the current trainer. This polling sequence expects hardware-owned ready and clock-switch status bits to change while the code is running, so it is not a pasteable trainer replacement for trainer_clock_init_72mhz().

/* Full-register STM32F103 example: HSE 8 MHz -> PLL x9 -> SYSCLK 72 MHz */
FLASH->ACR |= 0x2u;                 /* FLASH latency = 2 before 72 MHz */

RCC->CR |= (1u << 16);             /* HSEON: HSE source ON */
while ((RCC->CR & (1u << 17)) == 0u) { }   /* HSERDY: HSE stable */

{
    uint32_t cfgr = RCC->CFGR;
    cfgr &= ~((1u << 16) | (1u << 17) | (0xFu << 18) | (0xFu << 4) | (0x7u << 8) | (0x7u << 11) | (0x3u << 14));
    cfgr |=
        (1u << 16) |               /* PLLSRC = HSE: HSE -> PLL path */
        (0u << 17) |               /* PLLXTPRE = /1 */
        (7u << 18) |               /* PLLMUL = x9 */
        (0u << 4)  |               /* HPRE = /1 */
        (4u << 8)  |               /* PPRE1 = /2 */
        (0u << 11) |               /* PPRE2 = /1 */
        (2u << 14);                /* ADCPRE = /6 */
    RCC->CFGR = cfgr;
}

RCC->CR |= (1u << 24);             /* PLLON: PLL source ON */
while ((RCC->CR & (1u << 25)) == 0u) { }   /* PLLRDY: PLL stable */

RCC->CFGR = (RCC->CFGR & ~0x3u) | 0x2u;    /* SW = PLL */
while (((RCC->CFGR >> 2) & 0x3u) != 0x2u) { }   /* SWS = PLL */

This example shows the full-device clock-source path using RCC_CR, RCC_CFGR, and FLASH_ACR. Read it along the Figure 1 path: HSE -> PLLXTPRE -> PLL -> SW -> SYSCLK -> AHB/APB/ADC Prescaler. For the HSE 8 MHz -> PLL x9 -> 72 MHz route, PLLSRC = 1 selects HSE as the PLL input. The trainer helper performs the equivalent setup and explicitly writes the ready/status bits because no automatic oscillator or PLL state transition is modeled; use that helper for code that must run inside one user_init() phase.