STM32F103 RCC Clock Control Reference Chapter

Document scope

This chapter follows the official STM32F103 document split: the datasheet provides the big clock-tree view, while RM0008 explains the control registers, prescalers, and peripheral enable sequence. Trainer-executable examples are kept separate in Chapter 9.

1 RCC overview

On STM32F103, RCC performs three jobs. First, it decides which oscillator or PLL output becomes SYSCLK. Second, it divides that system clock into the AHB and APB bus clocks. Third, it enables or disables the bus clock that reaches each peripheral register block.

• HSI, HSE, and PLLCLK are SYSCLK candidates.
• SYSCLK feeds the AHB prescaler to produce HCLK.
• HCLK feeds the APB1 and APB2 prescalers to produce PCLK1 and PCLK2.
• Peripheral registers become readable and writable only after the relevant RCC enable bit is active on real hardware.

2 Clock tree overview

Figure 1. Reconstructed STM32F103 RCC clock-tree slice

Source reconstruction: STM32F103 datasheet (DS5319 Rev 20, Figure 2. Clock tree) and RM0008 Rev 21, Figure 8. Clock tree

The official documents place clock distribution before register details. That order matters because RCC_CR and RCC_CFGR only make sense after the reader can see where SYSCLK, HCLK, PCLK1, PCLK2, and ADCCLK come from.

2.1 Register callouts in Figure 1

PA2, PA3, and PA4 belong to GPIOA; PB0 and PB1 belong to GPIOB. Both GPIO port clocks are opened from RCC_APB2ENR on the PCLK2 side, not from PCLK1. PCLK1 is the APB1 side used here for TIM2.

• After reset, the internal 8 MHz RC oscillator (HSI) is the default CPU clock.
• AHB and APB2 can run up to 72 MHz.
• APB1 must stay at or below 36 MHz.
• Timer clocks follow the hardware x2 rule whenever the APB prescaler is not 1.

3 Derived clocks and important exceptions

4 RCC register map

Official base address: RCC = 0x40021000. Trainer pointer base: RCC = 0x1800. The trainer pointer is intentionally compact; do not infer official RCC_CR or RCC_CFGR pointer layout from it.

Figure 2. Representative RCC enable-register split across AHB, APB2, and APB1

Source reconstruction: RM0008 Rev 21, Sections 7.3.6 through 7.3.8. Trainer-highlighted bits show the currently exposed subset.

5 Clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83

RCC_CR is the "turn it on and wait until ready" register. Each oscillator or PLL enable bit has a matching ready status bit, so software can confirm that the source is stable before routing it into SYSCLK.

6 Clock configuration register (RCC_CFGR)

Address offset: 0x04
Reset value: 0x00000000

RCC_CFGR is the "which clock do I select and how do I divide it" register. The official RM0008 wording makes a clean distinction: RCC_CR enables sources, while RCC_CFGR routes and scales them.

6.1 Clock-tree bit and field summary

7 AHB/APB enable registers

7.3 APB2 peripheral clock enable register (RCC_APB2ENR)

Address offset: 0x18
Reset value: 0x00000000

Example whole-register write: RCC->APB2ENR = 0x0000020D

7.4 APB1 peripheral clock enable register (RCC_APB1ENR)

Address offset: 0x1C
Reset value: 0x00000000

Example whole-register write: RCC->APB1ENR = 0x00000001

8 Programming sequences

Official STM32F103 clock-source switching uses RCC_CR, RCC_CFGR, and FLASH_ACR. The current trainer code path keeps execution narrower and uses the APB enable registers directly.

9 Student register guide and code examples

9.1 Which RCC registers the student should look at

9.2 Current trainer route and enable examples

9.3 Current trainer code example

/* Current trainer example: enable only the APB gates that the lab needs */
RCC->APB2ENR |= (1u << 0);   /* AFIOEN: PCLK2 alternate-function helper gate */
RCC->APB2ENR |= (1u << 2);   /* IOPAEN: PCLK2 -> GPIOA gate */
RCC->APB2ENR |= (1u << 3);   /* IOPBEN: PCLK2 -> GPIOB gate */
RCC->APB2ENR |= (1u << 9);   /* ADC1EN: PCLK2 -> ADC1 interface gate */
RCC->APB1ENR |= (1u << 0);   /* TIM2EN: PCLK1 -> TIM2 gate */

This is the compact RCC code path students use most often in the current trainer. It enables the APB2 and APB1 peripheral register blocks needed by the visible GPIO, ADC, EXTI helper, and TIM2 routes.

9.4 Full STM32F103 example when every register is available

/* Full-register STM32F103 example: HSE 8 MHz -> PLL x9 -> SYSCLK 72 MHz */
FLASH_ACR |= 0x2u;                  /* FLASH latency = 2 before 72 MHz */

RCC->CR |= (1u << 16);             /* HSEON: HSE source ON */
while ((RCC->CR & (1u << 17)) == 0u) { }   /* HSERDY: HSE stable */

{
    uint32_t cfgr = RCC->CFGR;
    cfgr &= ~((1u << 16) | (1u << 17) | (0xFu << 18) | (0xFu << 4) | (0x7u << 8) | (0x7u << 11) | (0x3u << 14));
    cfgr |=
        (1u << 16) |               /* PLLSRC = HSE: HSE -> PLL path */
        (0u << 17) |               /* PLLXTPRE = /1 */
        (7u << 18) |               /* PLLMUL = x9 */
        (0u << 4)  |               /* HPRE = /1 */
        (4u << 8)  |               /* PPRE1 = /2 */
        (0u << 11) |               /* PPRE2 = /1 */
        (2u << 14);                /* ADCPRE = /6 */
    RCC->CFGR = cfgr;
}

RCC->CR |= (1u << 24);             /* PLLON: PLL source ON */
while ((RCC->CR & (1u << 25)) == 0u) { }   /* PLLRDY: PLL stable */

RCC->CFGR = (RCC->CFGR & ~0x3u) | 0x2u;    /* SW = PLL */
while (((RCC->CFGR >> 2) & 0x3u) != 0x2u) { }   /* SWS = PLL */

This example shows the full-device clock-source path using RCC_CR, RCC_CFGR, and FLASH_ACR. Read it along the Figure 1 path: HSE -> PLLXTPRE -> PLL -> SW -> SYSCLK -> AHB/APB/ADC Prescaler. For the HSE 8 MHz -> PLL x9 -> 72 MHz route, PLLSRC = 1 selects HSE as the PLL input.