TIM2 PWM Reference Chapter

1 Official reference basis

2 PWM generation path

Figure 1. TIM2 PWM generation path and fixed PA2 trainer route

Source reconstruction from RM0008 Rev 21 Figure 126, Figure 127, Figure 130, timer PWM register text in Section 15, and DS5319 Rev 20 Table 5. Reconstructed drawing; no vendor PDF image was pasted.

In official PWM mode 1, the output reference is active while CNT < CCRx and inactive for the rest of the period, subject to polarity and output enable settings. In PWM mode 2, the active/inactive relation is inverted. With an up-counting timer, the counter clock is TIMxCLK / (PSC + 1), the PWM period is approximately (ARR + 1) / counter_clock, and the active-high duty ratio is approximately CCR / (ARR + 1).

The trainer does not implement a cycle-accurate PSC/ARR/CNT waveform engine. Instead, it stores the visible duty command in TIM2_CCR1 as 0..100 percent and renders an average PA2 / PWM_OUT value in the Pin, Graph, Schematic, Mission, and Log views. Read TIM2_CCR1 here as the trainer duty command, not as proof that PA2 is official TIM2_CH1. On real STM32F103 hardware, PA2 PWM belongs to TIM2_CH3 and would be controlled through the channel-3 compare path, including TIM2_CCR3.

3 Pin and clock routing

4 Register map and simulated subset

4.1 Compact trainer register map

5 Register descriptions

5.1 Capture / compare enable register (TIM2_CCER)

Trainer address offset: 0x00. Reset value: 0x00000000.

Bit 0 CC1E: Enables the trainer PWM output gate when set to 1 and the TIM2 clock is enabled. In this chapter it is the compact trainer gate for PA2 / PWM_OUT, not an official PA2 channel-1 gate.

5.2 Capture / compare register 1 (TIM2_CCR1)

Trainer address offset: 0x04. Reset value: 0x00000000.

Bits 6:0 DUTY: Trainer duty command. 0 renders 0% and 100 renders 100% average output. Official PA2 channel-3 PWM would use TIM2_CCR3; the trainer keeps this value in TIM2_CCR1 as a compact alias.

6 Student register guide and code examples

6.1 Current trainer code example

• Enable RCC->APB2ENR.AFIOEN and RCC->APB2ENR.IOPAEN before relying on the GPIO/alternate-function path.
• Enable RCC->APB1ENR.TIM2EN before relying on TIM2 register effects.
• Use alternate-function push-pull as the official GPIO reference mode. The trainer observes the simplified PA2 / PWM_OUT route.
• Write the trainer duty command to TIM2_CCR1, then set TIM2_CCER.CC1E; this is the trainer alias for PA2 / PWM_OUT, not the official PA2 channel map.

RCC->APB2ENR |= (1u << 0);   /* AFIOEN */
RCC->APB2ENR |= (1u << 2);   /* IOPAEN */
RCC->APB1ENR |= (1u << 0);   /* TIM2EN */

/* PA2 trainer route: use AF push-pull style setup as the hardware reference. */
GPIOA->CRL &= ~(0xFu << 8);
GPIOA->CRL |=  (0xBu << 8);

TIM2->CCR1 = 65u;            /* trainer duty percent */
TIM2->CCER |= (1u << 0);     /* trainer output gate */

Read this flow as RCC gate -> GPIO route -> duty register -> output gate -> PA2 / PWM_OUT. The visible proof appears in Register View TIM2_CCR1/TIM2_CCER, Pin View PWM_OUT, and Graph View PA2 / PWM_OUT.

6.2 Full STM32F103 example when every timer register is available

• Use PSC and ARR to define timer frequency and period.
• Use CCMR1.OC1M to select PWM mode and CCMR1.OC1PE for preload.
• Use CCER.CC1E to open the channel output and CR1.CEN to run the counter.
• Keep the official pin truth separate: TIM2_CH1 is on PA0 or remapped PA15, while PA2 is TIM2_CH3.

RCC->APB2ENR |= (1u << 0);   /* AFIOEN */
RCC->APB2ENR |= (1u << 2);   /* IOPAEN */
RCC->APB1ENR |= (1u << 0);   /* TIM2EN */

/* Official TIM2_CH1 example on PA0 */
GPIOA->CRL &= ~(0xFu << 0);
GPIOA->CRL |=  (0xBu << 0);   /* PA0 AF push-pull */

TIM2->PSC = 71u;               /* 72 MHz / (71 + 1) = 1 MHz counter clock */
TIM2->ARR = 999u;              /* 1 kHz PWM period */
TIM2->CCR1 = 250u;             /* 25% duty */
TIM2->CCMR1 = (6u << 4) | (1u << 3);   /* PWM mode 1, preload */
TIM2->CCER |= (1u << 0);      /* CC1E */
TIM2->CR1 |= (1u << 7) | (1u << 0);    /* ARPE | CEN */

This full example explains the official timer path behind Figure 1, but the current pasteable trainer code remains the shorter example above.

6.3 Simulator alignment notes