TIM2 PWM Reference Chapter

1 Official reference basis

2 PWM generation path

Reconstructed from RM0008 Rev 21 Figure 100, General-purpose timer block diagram, and scoped to the current simulator/runtime contract. The figure keeps the official shared counter/compare structure, representative CC1 input-selection MUX, IC1PS, CC1I/CC2I, and OC1REF/OC2REF signal language. Blue marks the supported time base; yellow marks the current implementation CCR1 -> PWM_OUT and TIM2_CC2 -> ADC routes; grey marks reference-only behavior. The current implementation ADC branch is the modeled TIM2_CC2 event selected by ADC_CR2.EXTSEL=011 + EXTTRIG, not TRGO. The full trigger/slave block and unused channel lanes are intentionally omitted from this principle figure and remain reference-manual concepts.

CC1I/CC2I identify the official capture/compare interrupt or DMA request outputs, and U identifies the update event. They preserve RM0008 signal language for reading the figure, but their request/flag side effects are Reference-only in the current implementation.

This chapter is intentionally TIM2-only. The RM0008 TIM1/TIM8 advanced-control-only repetition counter, dead-time/break, complementary-output, and trigger/slave paths are Reference-only; the current implementation exposes an executable TIM2 focused register/header/UI path.

In official PWM mode 1, the output reference is active while CNT < CCRx and inactive for the rest of the period, subject to polarity and output enable settings. In PWM mode 2, the active/inactive relation is inverted. With an up-counting timer, the counter clock is TIMxCLK / (PSC + 1), the PWM period is approximately (ARR + 1) / counter_clock, and the active-high duty ratio is approximately CCR / (ARR + 1).

The trainer derives TIM2CLK from the modeled RCC clock tree, then advances CNT by elapsed timer cycles after the PSC + 1 division. The PWM period and duty therefore follow TIM2CLK / ((PSC + 1) × (ARR + 1)) and CCR1 / (ARR + 1). Board Lab pin routes renders the average PA2 / PWM_OUT voltage; Graph exposes PWM toggle and average probes, while Log records the derived frequency and period. Figure 1 is the only principle figure: it connects the time base to the trainer's observable CCR1 PWM and CCR2 ADC-trigger routes. On real hardware, preload bits and EGR.UG control shadow-register transfers; those side effects remain reference-only in the trainer. The official pin truth remains: PA2 is TIM2_CH3, while the trainer uses its fixed TIM2_CCR1 route. For a step-by-step ARR/CNT rollover and CNT/CCR1 compare example, continue to the TIM2/PWM User Description learning appendix.

3 Pin and clock routing

3.1 PA2 GPIO nibble before PWM output

The full GPIO nibble table is in the GPIO Register Datasheet. The PA2 field write is GPIOA->CRL = (GPIOA->CRL & ~(0xFu << 8)) | (0xBu << 8).

4 Register map and simulated subset

4.1 Complete official TIM2 register map

RM0008 Rev 21 Table 88 defines the full TIM2-to-TIM5 layout. Absolute addresses below use TIM2 base 0x40000000 + offset. Official reset values stay separate from trainer-specific reset and support notes.

5 Register descriptions

Each official TIM2 register now has its own address/reset line, 32-bit field layout, field table, and current Trainer boundary. Registers marked 미지원 remain here for RM0008 navigation and must not be read as executable Trainer features.

5.1 Control register 1 (TIM2_CR1)

Address offset: 0x00   Address: 0x40000000   Reset value: 0x00000000

5.2 Control register 2 (TIM2_CR2)

Address offset: 0x04   Address: 0x40000004   Reset value: 0x00000000

5.3 Slave mode control register (TIM2_SMCR)

Address offset: 0x08   Address: 0x40000008   Reset value: 0x00000000

5.4 DMA / interrupt enable register (TIM2_DIER)

Address offset: 0x0C   Address: 0x4000000C   Reset value: 0x00000000

5.5 Status register (TIM2_SR)

Address offset: 0x10   Address: 0x40000010   Reset value: 0x00000000

5.6 Event generation register (TIM2_EGR)

Address offset: 0x14   Address: 0x40000014   Reset value: 0x00000000

5.7 Capture / compare mode register 1 (TIM2_CCMR1)

Address offset: 0x18   Address: 0x40000018   Reset value: 0x00000000

Output-compare view when CC1S/CC2S = 00:

Input-capture overlay when a channel's CCxS != 00:

Shared OCxM decoder: 000 frozen, 001 set active on match, 010 set inactive, 011 toggle, 100 force inactive, 101 force active, 110 PWM mode 1, 111 PWM mode 2. In up-counting PWM mode 1, OCxREF is active while CNT < CCRx; mode 2 inverts that relation.

5.8 Capture / compare mode register 2 (TIM2_CCMR2)

Address offset: 0x1C   Address: 0x4000001C   Reset value: 0x00000000

Output-compare view for channels 4 and 3:

Input-capture overlay for channels 4 and 3:

5.9 Capture / compare enable register (TIM2_CCER)

Address offset: 0x20   Address: 0x40000020   Reset value: 0x00000000

15:14 are Reserved in RM0008; bits 31:16 are also Reserved and must remain at reset value.

5.10 Counter register (TIM2_CNT)

Address offset: 0x24   Address: 0x40000024   Reset value: 0x00000000

5.11 Prescaler register (TIM2_PSC)

Address offset: 0x28   Address: 0x40000028   Reset value: 0x00000000

5.12 Auto-reload register (TIM2_ARR)

Address offset: 0x2C   Address: 0x4000002C   Official reset value: 0x0000FFFF   Trainer lesson reset: 0x00000063

5.13 Capture / compare register 1 (TIM2_CCR1)

Address offset: 0x34   Address: 0x40000034   Reset value: 0x00000000

5.14 Capture / compare register 2 (TIM2_CCR2)

Address offset: 0x38   Address: 0x40000038   Reset value: 0x00000000

5.15 Capture / compare register 3 (TIM2_CCR3)

Address offset: 0x3C   Address: 0x4000003C   Reset value: 0x00000000

5.16 Capture / compare register 4 (TIM2_CCR4)

Address offset: 0x40   Address: 0x40000040   Reset value: 0x00000000

5.17 DMA control register (TIM2_DCR)

Address offset: 0x48   Address: 0x40000048   Reset value: 0x00000000

5.18 DMA address for full transfer (TIM2_DMAR)

Address offset: 0x4C   Address: 0x4000004C   Reset value: 0x00000000

6 Student register guide and code examples

6.1 Current trainer code example

• Enable RCC->APB2ENR.IOPAEN before configuring GPIOA. Enable AFIOEN only if code accesses AFIO_MAPR to select a remapped timer pin.
• Enable RCC->APB1ENR.TIM2EN before relying on TIM2 register effects.
• Use alternate-function push-pull as the official GPIO reference mode. The trainer observes the simplified PA2 / PWM_OUT route.
• Write the trainer duty command to TIM2_CCR1, set TIM2_CCER.CC1E, then set TIM2_CR1.CEN; this is the trainer alias for PA2 / PWM_OUT, not the official PA2 channel map.

void user_init(void)
{
    RCC->APB2ENR |= (1u << 2);   /* IOPAEN */
    RCC->APB1ENR |= (1u << 0);   /* TIM2EN */

    /* PA2 trainer route: AF push-pull style hardware reference. */
    GPIOA->CRL &= ~(0xFu << 8);
    GPIOA->CRL |=  (0xBu << 8);

    TIM2->PSC = 0u;
    TIM2->ARR = 99u;
    TIM2->CCR1 = 60u;            /* 60 / (99 + 1) = 60% */
    TIM2->CCR2 = 30u;            /* emits TIM2_CC2; ADC accepts only when configured */
    TIM2->CCER |= (1u << 0);    /* trainer output gate */
    TIM2->CR1 |= (1u << 0);     /* CEN */
}

void user_loop(void)
{
}

Read this flow as RCC gate -> GPIO route -> duty register -> output gate -> CEN -> PA2 / PWM_OUT. The register-value behavior above is enough to review the timer event itself. ADC conversion additionally requires ADC1EN, PA1 analog mode, SQR3 channel 1, and ADC_CR2.EXTSEL=011 + EXTTRIG; the complete executable path is in the TIM2/PWM User Description and ADC User Description.

6.2 Full STM32F103 reference example

Reference-only on real STM32F103: This example assumes that the clock tree has already produced TIM2CLK = 72 MHz (for example, 72 MHz SYSCLK with APB1 prescaled to 36 MHz, so the TIM2 clock is doubled). The focused trainer API omits CCMR1 and EGR, so use Section 6.1 for executable trainer code.

• Use PSC and ARR to define timer frequency and period.
• Use CCMR1.OC1M to select PWM mode and CCMR1.OC1PE for preload.
• Use CCER.CC1E to open the channel output and CR1.CEN to run the counter.
• Keep the official pin truth separate: TIM2_CH1 is on PA0 or remapped PA15, while PA2 is TIM2_CH3.

RCC->APB2ENR |= (1u << 2);   /* IOPAEN: default PA0 path */
RCC->APB1ENR |= (1u << 0);   /* TIM2EN */

/* Official TIM2_CH1 example on PA0 */
GPIOA->CRL &= ~(0xFu << 0);
GPIOA->CRL |=  (0xBu << 0);   /* PA0 AF push-pull */

TIM2->PSC = 71u;               /* 72 MHz / (71 + 1) = 1 MHz counter clock */
TIM2->ARR = 999u;              /* 1 kHz PWM period */
TIM2->CCR1 = 250u;             /* 25% duty */
TIM2->CCMR1 = (6u << 4) | (1u << 3);   /* PWM mode 1, preload */
TIM2->EGR = 1u;                /* UG: load prescalers/preloads before CEN */
TIM2->CCER |= (1u << 0);      /* CC1E */
TIM2->CR1 |= (1u << 7) | (1u << 0);    /* ARPE | CEN */

This full example uses the default PA0 channel-1 path. Enable AFIOEN before writing AFIO_MAPR only when selecting the remapped PA15 path. The current pasteable trainer code remains the shorter example above.

6.3 Simulator alignment notes