USART1 Datasheet

1 Official reference basis

1.1 RM0008 Rev 21 practical reading order

Page numbers below are the printed page numbers shown in the RM0008 footer. A PDF viewer can differ by one or two pages, so use the Section title as the second search key.

2 USART1 architecture

2.1 Follow the two data lanes

Figure 1. Practice-first USART1 data path: clock, CR1 enables, BRR, DR, shift registers, and SR flags

Source reconstruction from RM0008 Rev 21 Figure 279, Sections 27.3.2-27.3.4, RCC/AFIO controls, and DS5319 Rev 20, Table 5. The vendor figure was reduced to the first-lab lanes; special modes, DMA, flow control, and interrupt routing were intentionally omitted.

On the official device, TX writes go through USART_DR into the transmit shift register and drive PA9 / USART1_TX when the peripheral, transmitter, and pin path are enabled. RX samples PA10 / USART1_RX, loads USART_DR, and sets SR.RXNE until software reads the data register.

The trainer models a lesson-specific receive frame as CMD:DATA packed into USART1_DR. A modeled USART1_DR read consumes RX data. Writing USART1_DR records the low byte as trainer transmit data and leaves SR.TXE and SR.TC set after the immediate simulated transmission.

2.2 Read one frame as 8-N-1

Figure 2. First-lab 8-N-1 frame using 0x55 as the LSB-first example byte

Source reconstruction from RM0008 Rev 21 Figure 280 and Section 27.3.1. Only the asynchronous 8-bit, no-parity, one-stop-bit path used by the lab is shown.

When parity is enabled on the real device, parity occupies the word length: M=0 gives seven data bits plus parity, while M=1 gives eight data bits plus parity.

2.3 Use TXE for the next byte and TC for the final finish

Figure 3. TXE becomes ready before TC becomes complete

Source reconstruction from RM0008 Rev 21 Sections 27.3.2 and 27.6.1. The timeline isolates the TDR, shift-register, TX pin, TXE, and TC relationship from the full USART block.

3 Clock and pin routing

3.1 PA9 / PA10 GPIO nibble values

See the GPIO Register Datasheet for the complete nibble table.

3.2 Clock gates for default and remapped pins

4 Register map and reset values

The complete block below follows RM0008 Rev 21 Table 198. Absolute addresses use USART1 base 0x40013800 + offset; trainer aliases do not change the official offsets.

The USART1_DR reset discrepancy is handled in the owning register subsection below: the detailed RM0008 register description is the reset authority, while the trainer deterministic zero is a separate support fact.

4.1 Datasheet fields to current code and legacy executable aliases

Legacy executable aliases are kept only as a current-code compatibility bridge. No separate Registers alias row is rendered.

5 Register descriptions

5.1 Control register 1 (USART1_CR1)

Address offset: 0x0C   Address: 0x4001380C   Reset value: 0x00000000

UE bit 13 enables USART1, TE bit 3 enables transmit, and RE bit 2 enables receive. Official bit 0 is SBK; the trainer also accepts it as a legacy RX enable alias, so new code should use UE | RE.

5.2 Status register (USART1_SR)

Address offset: 0x00   Address: 0x40013800   Reset value: 0x000000C0

rc_w0 means read/clear by writing 0; writing 1 does not clear the official flag. Error/idle flags marked R are cleared by the documented status-then-data read sequence, not by treating the entire register as ordinary read-only storage.

The focused MMIO accepts a stored SR word but does not reproduce official per-field rc_w0 masking. Do not teach raw SR writes as the trainer equivalent of RM0008 clearing rules; use USART1_DR read for the supported RX consume path.

5.3 Data register (USART1_DR)

Address offset: 0x04   Address: 0x40013804   Official reset value: Undefined. Current trainer initialization: 0x00000000.

RM0008 Table 198 draws a zero reset row for the map summary, while the detailed Section 27.6.2 register description states Reset value: Undefined. Firmware should not read DR before RXNE or assume power-on contents. The trainer's zero initialization is deterministic UI state, not official silicon reset behavior.

5.4 Baud-rate register (USART1_BRR)

Address offset: 0x08   Address: 0x40013808   Reset value: 0x00000000

In official oversampling-by-16 mode, USARTDIV = fCK / (16 * baud) and BRR stores mantissa and fraction fields. For a 72 MHz USART clock and 9600 bps, USARTDIV = 468.75 and the common reference value is 0x1D4C. The trainer requires this register to be nonzero, while the UI keeps a 9600 bps protocol label and uses display animation timing that is not derived from BRR.

5.5 Reference-only USART control registers (USART1_CR2, USART1_CR3, USART1_GTPR)

These registers are official RM0008 USART1 registers. The current trainer does not expose them through the focused USART_TypeDef, MMIO list, or Registers view.

6 Student register guide and code examples

6.1 Current trainer code example

• For the current RX-only example, enable IOPAEN and USART1EN, then configure PA10 as input. PA9 remains official TX reference truth but is not initialized by the executable example.
• Enable AFIOEN only before accessing AFIO_MAPR for the PB6/PB7 remap; that remap path is not exposed by the focused trainer header.
• Read the real pin truth as PA9 alternate-function output and PA10 input. The fixed Trainer route enforces those GPIOA_CRH modes; the receive example uses independent External UART TX → PA10 / UART_RX.
• Write USART1_BRR before enabling the USART in F103-style setup code.
• Set only USART1_CR1.UE and USART1_CR1.RE. The executable example leaves TE=0 and never writes USART1_DR.
• Poll USART1_SR.RXNE, then use USART1_DR read to consume the Trainer frame and execute the modeled read side effect.

void user_init(void)
{
    trainer_clock_init_72mhz();
    RCC->APB2ENR = RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_ADC1EN;
    RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
    RCC->APB1ENR = RCC_APB1ENR_TIM2EN;
    GPIOA->CRH = (GPIOA->CRH & ~(0xFu << 8)) | (0x4u << 8); /* PA10 RX */
    USART1->BRR = 0x1D4Cu;
    USART1->CR1 = USART1_CR1_UE | USART1_CR1_RE;
}

void user_loop(void)
{
    if ((read_reg(USART1_SR) & (1u << 5)) != 0u) {
        uint32_t frame = read_reg(USART1_DR); /* Trainer-only CMD:DATA packed word */
        uint32_t cmd = (frame >> 8) & 0xFFu;
        uint32_t data = frame & 0xFFu;
        watch_u32("uart_cmd", cmd);
        watch_u32("uart_data", data);
    }
}

Read this flow as IOPAEN + USART1EN -> PA10 input -> BRR -> UE/RE -> RXNE poll -> DR read. The register-value behavior above is enough to review USART1 code; learner-facing UI confirmation is mapped in the USART1/UART User Description.

6.2 Full STM32F103 example when every USART register is available

Reference-only on real STM32F103: The focused trainer header omits USART1_CR2 and USART1_CR3, and the trainer does not model full pin muxing or hardware polling delays. Use Section 6.1 for executable trainer code.

• Keep the same core bring-up path: RCC->APB2ENR.USART1EN, BRR, and CR1.
• Use the official pin truth: PA9 = USART1_TX and PA10 = USART1_RX, with optional remap to PB6/PB7.
• Expand into frame-format and stop-bit control through CR2 and advanced flow control through CR3 when the full device path needs them.

RCC->APB2ENR |= (1u << 2);   /* IOPAEN: default PA9/PA10 path */
RCC->APB2ENR |= (1u << 14);  /* USART1EN */

/* Official STM32F103 pin setup example */
GPIOA->CRH &= ~((0xFu << 4) | (0xFu << 8));
GPIOA->CRH |=  (0xBu << 4);   /* PA9  AF push-pull */
GPIOA->CRH |=  (0x4u << 8);   /* PA10 floating input */

USART1->BRR = 0x1D4Cu;
USART1->CR1 = (1u << 13) | (1u << 3) | (1u << 2);  /* UE | TE | RE */
USART1->CR2 = 0u;                                      /* 1 stop bit */
USART1->CR3 = 0u;                                      /* no flow control */

while ((USART1->SR & (1u << 7)) == 0u) { }            /* TXE */
USART1->DR = 'A';
while ((USART1->SR & (1u << 6)) == 0u) { }            /* TC */

This full example uses the default PA9/PA10 mapping, so it does not enable AFIO. For PB6/PB7 remap, first enable AFIOEN and IOPBEN, then write AFIO_MAPR.USART1_REMAP and configure GPIOB. That remap setup is reference-only in the focused trainer.

6.3 Simulator alignment notes