Universal synchronous/asynchronous receiver transmitterUSART1 Chapter

USART1 Datasheet

STM32F103 USART1 SR/DR/BRR contract and PA9/PA10 routing

Document ID: USART1-DS001
Revision: Rev 1.1
Registers: CR1 / SR / DR / BRR
Primary refs: DS5319 / RM0008

The STM32F103 USART1 block is clocked from APB2, uses USART1_CR1 for UE, TE, and RE, reports status in USART_SR, transfers through USART_DR, and stores the baud divider in USART_BRR. The compact trainer aliases are documented in the final student section.

Official reference basis
USART1 architecture
Clock and pin routing
Register map and simulated subset
Register descriptions
Student register guide and code examples

1 Official reference basis

Source	Relevant item	Use in this chapter
STM32F103x8/xB datasheet DS5319 Rev 20	Table 5, alternate functions	PA9 is USART1_TX, PA10 is USART1_RX. Remap can place TX/RX on PB6/PB7.
STM32F10xxx reference manual RM0008 Rev 21	RCC section 7.3.7	RCC->APB2ENR.USART1EN, IOPAEN, and AFIOEN gate the peripheral and pin path.
RM0008 Rev 21, Section 27	USART registers and status flags	USART_SR, USART_DR, USART_BRR, and USART_CR1 define the basic transmit/receive contract.
RM0008 Rev 21, Section 27	Status and control bits	RXNE, TXE, TC, UE, TE, and RE are the relevant F103 bits.

2 USART1 architecture

Figure 1. USART1 transmit/receive path and trainer aliases

Source reconstruction from RM0008 Rev 21 Figure 279 USART block diagram, Section 27 USART data path/status behavior, and DS5319 Rev 20, Table 5 pin mapping. Reconstructed drawing; no vendor PDF image was pasted.

On the official device, TX writes go through USART_DR into the transmit shift register and drive PA9 / USART1_TX when the peripheral, transmitter, and pin path are enabled. RX samples PA10 / USART1_RX, loads USART_DR, and sets SR.RXNE until software reads the data register.

The trainer models a lesson-specific receive frame as CMD:DATA packed into USART1_DR. A trainer-observable read_reg(USART1_DR) consumes RX data. Writing USART1_DR appends a byte to the UART TX log and leaves SR.TXE and SR.TC set after the immediate simulated transmission.

3 Clock and pin routing

Layer	Official STM32F103 fact	Current trainer contract
Clock	USART1 is on APB2. Enable RCC->APB2ENR.USART1EN.	The simulator rejects RX/TX effects when USART1EN is gated. The compact trainer path does not additionally inspect GPIOA_CRH.
GPIO	PA9 is TX alternate-function output. PA10 is RX input. PB6/PB7 are remap options.	The board exposes the fixed PA10 / USART1_RX / COMM_RX receive route and logs TX writes rather than drawing a separate PA9 wire. Full pin-mode setup is shown below as the STM32 reference path.
Baud	For oversampling by 16, USARTDIV = fCK / (16 * baud); BRR stores mantissa and fraction.	USART1_BRR is stored and displayed. UI waveform timing remains the fixed 9600 bps trainer timing.
Interrupts	USART status flags can drive interrupt requests when enabled.	The trainer exposes flags and logs; it does not emulate the full NVIC USART interrupt sequence.

4 Register map and simulated subset

Register	Current use	Main role	Read it together with
RCC_APB2ENR	Use now	Turns on USART1 for the compact trainer RX/TX effect. STM32-style examples also enable GPIOA and AFIO for the real pin path.	Section 3 clock/pin routing and Figure 1 pin interface.
USART1_BRR	Use now	Stores the baud divider value used for a normal STM32F103 bring-up sequence.	Figure 1 baud-rate generator block.
USART1_CR1	Use now	Enables the USART and TX/RX directions through UE, TE, and RE.	Figure 1 transmit/receiver control lanes.
USART1_SR	Use now	Shows RXNE, TXE, and TC so software knows when data is ready.	Figure 1 status flag box and External Comm / Log view.
USART1_DR	Use now	Receives packed trainer RX frames and records trainer TX bytes.	Figure 1 data-register block and Pin View COMM_RX.
USART1_ISR / USART1_RDR	Reference-visible	Legacy aliases kept for older lessons.	Register View alias mapping only; new code should prefer SR/DR.
USART1_CR2 / USART1_CR3	Full STM32F103 example	Hold frame format, stop-bit, DMA, and advanced USART controls in the full device model.	Official RM0008 Section 27 flow beyond the compact trainer subset.

4.1 Compact trainer register map

Offset	Primary register	Legacy alias	Reset value	Current use	Description
0x30	USART1_CR1	-	0x00000000	Use now	Control register. Official UE, TE, and RE bits are accepted; legacy bit 0 also enables RX for older lessons.
0x34	USART1_SR	USART1_ISR	0x000000C0	Use now	Status register. TXE and TC reset set in the trainer; RXNE is set on new RX data.
0x38	USART1_DR	USART1_RDR	0x00000000	Use now	Data register. Read consumes RX; write records a TX byte in the trainer log.
0x3C	USART1_BRR	-	0x00000000	Use now	Baud-rate register. Stored for F103-style bring-up; fixed trainer waveform timing remains 9600 bps.

5 Register descriptions

5.1 Control register 1 (USART1_CR1)

Trainer offset: 0x30. Reset value: 0x00000000.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved																		UE	Reserved									TE	RE	Res	RXEN alias
-																		R/W	-									R/W	R/W	-	R/W

UE bit 13 enables USART1, TE bit 3 enables transmit, and RE bit 2 enables receive. Bit 0 is a trainer-only legacy RX enable alias.

5.2 Status register (USART1_SR)

Trainer offset: 0x34. Reset value: 0x000000C0.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved																								TXE	TC	RXNE	Res	ORE	Res	FE	RX ready alias
-																								R/W	R/W	R/W	-	R/W	-	R/W	R/W

RXNE bit 5 is set when a trainer RX frame is available. A trainer-observable read through read_reg(USART1_DR) clears RXNE and the legacy bit 0 ready alias. TXE bit 7 and TC bit 6 are set after an immediate simulated DR transmit write.

5.3 Data register (USART1_DR)

Trainer offset: 0x38. Reset value: 0x00000000.

Bits	Official role	Trainer behavior
15:8	Reserved or unused in a simple 8-bit frame read	Trainer command byte for the packed CMD:DATA frame.
7:0	Data byte read or transmit byte written through DR	Read returns trainer data byte; write appends this byte to the TX log.

5.4 Baud-rate register (USART1_BRR)

Trainer offset: 0x3C. Reset value: 0x00000000.

In official oversampling-by-16 mode, USARTDIV = fCK / (16 * baud) and BRR stores mantissa and fraction fields. For a 72 MHz USART clock and 9600 bps, USARTDIV = 468.75 and the common reference value is 0x1D4C. The trainer stores this value but keeps the waveform UI at fixed 9600 bps timing.

6 Student register guide and code examples

6.1 Current trainer code example

Enable USART1EN in RCC->APB2ENR for the compact trainer RX/TX effect. The longer STM32-style example below also enables AFIOEN and IOPAEN.
Read the real pin truth as PA9 alternate-function output and PA10 input. The current trainer observes fixed PA10 / COMM_RX and does not require GPIOA_CRH for the compact USART test.
Write USART1_BRR before enabling the USART in F103-style setup code.
Set USART1_CR1.UE and USART1_CR1.RE for RX; set TE to make USART1_DR writes visible in the TX log.
Poll USART1_SR.RXNE, then use read_reg(USART1_DR) to consume the trainer frame and make the read side effect visible to the simulator.

RCC->APB2ENR |= (1u << 14);  /* USART1EN: compact trainer RX/TX gate */

USART1->BRR = 0x1D4Cu;       /* 72 MHz / 9600 bps style reference */
USART1->CR1 = (1u << 13) | (1u << 3) | (1u << 2);  /* UE | TE | RE */

if ((read_reg(USART1_SR) & (1u << 5)) != 0) {
    uint32_t frame = read_reg(USART1_DR);
    uint32_t cmd = (frame >> 8) & 0xFFu;
    uint32_t data = frame & 0xFFu;
}

USART1->DR = 0x55u;          /* trainer TX log byte */

Read this flow as USART1EN -> BRR -> UE/TE/RE -> SR flag poll -> DR read/write. The visible proof appears in Register View USART1_CR1/USART1_SR/USART1_DR, Pin View COMM_RX, and the External Comm / Log panels.

6.2 Full STM32F103 example when every USART register is available

Keep the same core bring-up path: RCC->APB2ENR.USART1EN, BRR, and CR1.
Use the official pin truth: PA9 = USART1_TX and PA10 = USART1_RX, with optional remap to PB6/PB7.
Expand into frame-format and stop-bit control through CR2 and advanced flow control through CR3 when the full device path needs them.

RCC->APB2ENR |= (1u << 0);   /* AFIOEN */
RCC->APB2ENR |= (1u << 2);   /* IOPAEN */
RCC->APB2ENR |= (1u << 14);  /* USART1EN */

/* Official STM32F103 pin setup example */
GPIOA->CRH &= ~((0xFu << 4) | (0xFu << 8));
GPIOA->CRH |=  (0xBu << 4);   /* PA9  AF push-pull */
GPIOA->CRH |=  (0x4u << 8);   /* PA10 floating input */

USART1->BRR = 0x1D4Cu;
USART1->CR1 = (1u << 13) | (1u << 3) | (1u << 2);  /* UE | TE | RE */
USART1->CR2 = 0u;                                      /* 1 stop bit */
USART1->CR3 = 0u;                                      /* no flow control */

while ((USART1->SR & (1u << 7)) == 0u) { }            /* TXE */
USART1->DR = 'A';
while ((USART1->SR & (1u << 6)) == 0u) { }            /* TC */

This full example explains the official STM32F103 serial path behind Figure 1, while the shorter trainer example above remains the main pasteable code for the current trainer path.

6.3 Simulator alignment notes

View	Expected wording or behavior
Pin View	PA10 / USART1_RX / COMM_RX shows receive waveform state and USART1_SR.RXNE relation.
Register View	Use USART1_CR1, USART1_SR, USART1_DR, and USART1_BRR as primary names. Legacy USART1_ISR/USART1_RDR may appear only as aliases.
External Comm / Log	RX input sets RXNE and updates DR. Trainer read side effects are guaranteed through read_reg(USART1_DR). DR writes produce TX log entries and leave TXE/TC set.
Mission	RX enable may pass through official UE\|RE or the legacy bit 0 alias, but new examples should use the official F103 bits.

USART1 compact trainer subsetUSART1-DS001 Rev 1.1

USART1 Datasheet

Contents

1 Official reference basis

2 USART1 architecture

3 Clock and pin routing

4 Register map and simulated subset

4.1 Compact trainer register map

5 Register descriptions

5.1 Control register 1 (USART1_CR1)

5.2 Status register (USART1_SR)

5.3 Data register (USART1_DR)

5.4 Baud-rate register (USART1_BRR)

6 Student register guide and code examples

6.1 Current trainer code example

6.2 Full STM32F103 example when every USART register is available

6.3 Simulator alignment notes