VMD-MD01-Lite Motor Driver Datasheet

1 General description

VMD-MD01-Lite is an H-bridge motor-driver device intended for low-channel-count electromechanical actuation systems. The device receives an enable command, a direction command and a PWM drive command from an external controller, and converts these signals into a bidirectional power output across the motor terminals.

In addition to the power-output function, the driver monitors fault conditions and publishes a digital fault output. A current feedback path is also provided so that the system controller can observe load behavior or detect abnormal operating conditions.

This document is not the register chapter. The GPIOA, TIM2, and ADC1 chapters explain how the MCU produces or reads each signal; this chapter explains what each board-facing motor-driver signal means after those registers are set.

Figure 1A. HALL tab: shared drive path, Kelvin-connected 0.05 Ω shunt to PA1, and motor-integrated 3.3 V pull-up HALL_IN to PA6 / EXTI6

Source boundary: H-bridge command, output, and fault roles are reconstructed from ST VNH5019A-E and TI DRV8873 concepts. The raw low-side shunt and 3.3 V open-collector Hall adapter are the current Trainer implementation, not vendor pin claims. AFIO_EXTICR2.EXTI6=0000 selects PA6; other port sources and Hall transition counts are reference-only/Trainer plant assumptions because no Hall vendor device is selected.

Figure 1B. ANGLE tab: the same MCU, driver, motor, and shunt with only the feedback adapter changed to 3.3 V AS5600 analog OUT → PA6 / ADC1_IN6

Source boundary: the common AS5600 profile is 3.3 V mode, OUTS=00, and programmed MANG=180°, yielding 2048 distinct DAC steps across 0..180°. I²C programming, DIR, PWM output, and magnet diagnostics remain reference-only. The driver path and firmware remain shared with Figure 1A.

Figure 2. Reconstructed driver IC application circuit with ST-style support components, DIAG/EN, CS, OUTA/OUTB, VCC, VBAT, CP, GND, and motor load

Source reconstruction: ST VNH5019A-E Figure 5 on page 16, typical application circuit for DC to 20 kHz PWM operation with reverse-battery protection. Teal labels show the trainer-facing aliases; no vendor artwork is pasted.

2 Trainer signal summary

Reference drivers often expose a low-true nFAULT or DIAG pin and an IPROPI or CS current output. The board-facing MCU signal is intentionally named FAULT_IN. Driver control and conditioned fault logic use 0/3.3 V, PA1 / CURRENT_SENSE uses a 3.3 V ADC reference, and Motor A/B use the VM = 12 V power domain. The external PA10 UART alone retains a separate 0/5 V FT input contract. Source PDFs: VNH5019A-E and DRV8873-Q1.

3 Main features

• Single PWM input for proportional drive command
• Dedicated enable input and direction input
• Bidirectional H-bridge power stage with OUT_FWD and OUT_BW
• Board-facing digital fault input to the MCU, active high
• Direct 0.05 Ω low-side shunt sense path to ADC1 channel 1, with Kelvin/power/protection requirements for real hardware
• VM-domain Motor A/B output model: selected terminal average = D × VM; signed differential command = ±VM × D
• Support for stop, ready, running and fault operating states

4 Mode-specific trainer schematics

Figures 1A and 1B are the student-facing schematics for the two feedback tabs. Both keep the same MCU, H-bridge, motor, direct low-side shunt, fault path, and firmware contract. Only the motor-integrated PA6 feedback adapter changes.

5 Pin description

6 Operating states

7 Input-to-output truth table and waveforms

Figure 3. Input-to-output timing contract for STOP, CW, safe direction change, CCW, and FAULT

Source-derived layout: ST VNH5019A-E Figure 11 on pages 22-23 establishes the multi-lane input/PWM/output waveform reading order. Read input PWM/EN/DIR/FAULT lanes as 3.3 V logic and Motor A/B lanes as 0↔VM power switching; any legacy 5 V output-lane scale in the illustration is superseded by this VM-domain table. Timing is not copied vendor timing.

Figure 3 answers the literal HIGH/LOW sequence: EN LOW produces no output; EN HIGH + DIR LOW applies PWM-gated VM switching to Motor A; after PWM is set to zero, DIR HIGH applies the next PWM-gated VM switching to Motor B; FAULT_IN HIGH forces both effective outputs to zero. The Trainer does not model sub-cycle MOSFET dead time, recirculation, or detailed brake/coast current decay.

8 Fault indication and reset

Real reference drivers commonly expose an open-drain, low-true nFAULT or DIAG signal. The Trainer board contract inverts or conditions that signal so PA5 / FAULT_IN is active high: LOW means normal and HIGH means a conditioned 3.3 V fault. This board conversion is why the MCU-facing polarity differs from the source devices. Current fault classes are created only by manual Trainer injection; neither the raw shunt reading nor a simulated junction temperature automatically asserts them.

Figure 4. Reference low-true fault indication and Trainer active-high board conversion

Source reconstruction: VNH5019A-E Table 2 and pages 7-8 describe open-drain DIAG/EN fault reporting; page 16 Table 13 shows fault output action. DRV8873 Figure 17 on page 22 shows the nFAULT pull-up, and Table 13 on page 28 lists protection responses. The board-conditioning block is the local Trainer contract, not a claim about either vendor IC's internal circuit.

Figure 5. Representative fault shutdown, acknowledge, clear verification, and controlled restart timing

Source-derived layout: VNH5019A-E Figure 6 on page 17 establishes the fault-latch and input-transition reading order; DRV8873 Table 13 on page 28 shows that recovery can be automatic, retry-based, or latched by fault class and configuration. The FAULT ACK lane and next-tick PA5 confirmation are the current Trainer contract. Timing is logical and not to scale.

8.1 Reset and recovery behavior

8.2 Fault class mapping

8.3 Trainer reset sequence

/* 1) Safe stop first. */
TIM2->CCR1 = 0u;                    /* PA2 / PWM_OUT duty = 0% */
GPIOA->ODR &= ~GPIOA_DRV_EN_BIT;  /* PA3 / DRV_EN = LOW */

/* 2) Real hardware: remove the physical fault cause here. */

/* 3) Trainer-only acknowledge. The visible PA5 state updates on a later tick. */
VMD_MD01->FAULT = 0u;

/* 4-5) Restart only after both Trainer-visible fault views are clear. */
if ((VMD_MD01->FAULT == 0u) &&
    ((GPIOA->IDR & GPIOA_FAULT_IN_BIT) == 0u)) {
    GPIOA->ODR &= ~GPIOA_DRV_DIR_BIT; /* CW: DIR LOW */
    TIM2->CCR1 = 50u;                  /* 50% duty */
    GPIOA->ODR |= GPIOA_DRV_EN_BIT;    /* EN asserted last */
}

9 Student application notes

This final section links the board-facing driver signals back to the student-visible register and UI workflow. In the current trainer flow, the controller drives DRV_EN, DRV_DIR, and PWM_OUT, then checks FAULT_IN, CURRENT_SENSE, OUT_FWD, and OUT_BW. In Graph, the observable H-bridge output probes are labeled OUT_FWD toggle and OUT_BW toggle; each probe shows an average beside its live value because the trainer does not model sub-cycle bridge switching.

The CURRENT_SENSE signal is the raw voltage at the 0.05 Ω low-side shunt and is connected to PA1 / ADC1_IN1 using Kelvin sense traces. Real hardware must rate shunt power, protect the ADC, and account for low-side ground lift and unobserved recirculation/reverse current. The FAULT_IN signal returns to PA5 as a board-conditioned active-high 3.3 V GPIO input; its current causes are manually injected.

Student reading order: identify the board-facing signal name here, follow its function in Figure 1A or 1B through Figure 5, then return to the GPIOA, TIM2, or ADC1 chapter to see which MCU register path produces or observes it.

9.1 Week 2 ADC and driver-code contract

In the current training bench, CURRENT_SENSE is the 0.05 Ω raw low-side shunt voltage Kelvin-connected to PA1 / ADC1_IN1, and the board returns manually injected FAULT_IN to PA5 as an active-high 3.3 V diagnostic line. Vendor CS/IPROPI and automatic protection behavior remain reference-only.

9.2 System Trainer 공통 실행 예제

Paste this example directly into FW EDIT. It uses only symbols provided by training_api.h and keeps PWM at 0% with Driver Enable LOW whenever the fault input is active.

#include "training_api.h"

static void gpio_init(void)
{
    GPIOA->CRL = 0x40422B00u; /* GPIO User Description 4번: PA2 PWM, PA3·PA4 output, PA5 fault input */
    GPIOB->CRL &= ~0xFu;     /* 공통 하네스: PB0 / ADC1_IN8 NTC divider */
    if (TRAINER->FEEDBACK_MODE == TRAINER_FEEDBACK_ANGLE) {
        GPIOA->CRL &= ~(0xFu << 24); /* PA6 / ADC1_IN6 */
        EXTI->IMR &= ~EXTI_IMR_MR6;
    } else {
        GPIOA->CRL = (GPIOA->CRL & ~(0xFu << 24)) | (0x4u << 24); /* PA6 floating input */
        AFIO->EXTICR[1] &= ~(0xFu << 8); /* EXTICR2: EXTI6 = Port A / PA6 Hall */
        EXTI->IMR = EXTI_IMR_MR6;
        EXTI->RTSR = EXTI_RTSR_TR6;
        EXTI->FTSR = 0u;
        EXTI->PR = EXTI_PR_PR6;
        HALL->COUNT = 0u;
    }
    GPIOA->ODR &= ~(GPIOA_DRV_EN_BIT | GPIOA_DRV_DIR_BIT); /* GPIO UD 2번: EN·DIR LOW 안전 시작 */
}

static void pwm_init(void)
{
    TIM2->PSC = 11999u;          /* TIM User Description 2번: 6 kHz counter clock */
    TIM2->ARR = 99u;             /* TIM User Description 3번: 60 Hz PWM period */
    TIM2->CCR1 = 0u;             /* TIM User Description 4번: duty 0% 안전 시작 */
    TIM2->CCER = TIM2_CCER_CC1E; /* TIM User Description 4번: PWM output gate */
    TIM2->CR1 = TIM2_CR1_CEN;    /* TIM User Description 3번: counter 시작 */
}

static uint32_t fault_read(void)
{
    if ((GPIOA->IDR & GPIOA_FAULT_IN_BIT) != 0u) return 1u;
    if (VMD_MD01->FAULT != 0u) return 1u;
    return 0u;
}

static void motor_stop(void)
{
    TIM2->CCR1 = 0u;                   /* 먼저 PWM duty를 0%로 내립니다. */
    GPIOA->ODR &= ~GPIOA_DRV_EN_BIT; /* 그 다음 Driver Enable을 LOW로 내립니다. */
}

void user_init(void)
{
    trainer_clock_init_72mhz();             /* RCC User Description 1~4번 */
    RCC->APB2ENR = RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_ADC1EN | RCC_APB2ENR_USART1EN; /* 공통 MCU/센서/UART gate set */
    RCC->APB1ENR = RCC_APB1ENR_TIM2EN;     /* TIM User Description 1번: TIM2 gate */
    gpio_init();                            /* GPIO User Description 2번·4번 */
    pwm_init();                             /* TIM User Description 2~4번 */
    motor_stop();                           /* duty 0% → EN LOW 안전 정지 */
}

void user_loop(void)
{
    if (fault_read() != 0u) motor_stop();

    watch_u32("DRV_ENABLE", GPIOA->ODR & GPIOA_DRV_EN_BIT);
    watch_u32("DRV_DIRECTION", GPIOA->ODR & GPIOA_DRV_DIR_BIT);
    watch_u32("DRV_FAULT", fault_read());
    watch_u32("PWM_DUTY", TIM2->CCR1);
}