GPIOA Register Datasheet

1 General description

GPIOA is a 16-bit general-purpose I/O port. Each port bit can be programmed independently as a digital input, digital output, alternate-function output, or analog input, depending on the selected mode and configuration bits. The port provides separate input and output data paths, atomic bit set/reset access, and configuration lock capability.

GPIOA configuration is controlled through the low and high configuration registers (GPIOA_CRL and GPIOA_CRH). Runtime data access is performed through GPIOA_IDR, GPIOA_ODR, GPIOA_BSRR, GPIOA_BRR, and GPIOA_LCKR.

In the real STM32F103 clock tree, the GPIOA register block sits on the APB2 bus. That means the GPIO chapter should always be read together with RCC->APB2ENR.IOPAEN: without the port clock, CRL/CRH configuration and pad-level I/O behavior are not part of an active peripheral path.

This chapter keeps the GPIO chapter in a reference-manual style. Package pin and alternate-function facts remain in Section 5, while the mode figures below stay focused on the internal port-bit structure reconstructed from RM0008.

2 Main features

• 16 independently programmable port bits
• Input mode: analog, floating input, pull-up / pull-down input
• Output mode with programmable maximum speed: 10 MHz, 2 MHz, or 50 MHz
• Output structure: push-pull or open-drain
• Alternate-function output mode for timer, communication, and peripheral signals
• Input data sampling through GPIOA_IDR
• Output latch read/write through GPIOA_ODR
• Atomic bit set/reset through GPIOA_BSRR
• Optional reset-only path through GPIOA_BRR
• Configuration lock through GPIOA_LCKR

3 GPIO port architecture

Figure 1. Reconstructed GPIO port-bit architecture based on RM0008 Figure 13 and Figure 14

Source reconstruction from RM0008 Rev 21, GPIO port-bit architecture and bit set/reset model. Reconstructed drawing; no vendor PDF image was pasted.

4 I/O port bit configuration

Figure 2. Reconstructed input floating / pull-up / pull-down configuration based on RM0008 Figure 15

Source reconstruction from RM0008 Rev 21, Figure 15. Exact MODE/CNF values are stated in the surrounding tables.

Figure 3. Reconstructed output configuration based on RM0008 Figure 16

Source reconstruction from RM0008 Rev 21, Figure 16. Trainer output routes are documented separately in Section 8.

Figure 4. Reconstructed alternate-function configuration based on RM0008 Figure 17

Source reconstruction from RM0008 Rev 21, Figure 17. Alternate-function possibilities are separated from the current simulated subset.

Figure 5. Reconstructed high-impedance analog configuration based on RM0008 Figure 18

Source reconstruction from RM0008 Rev 21, Figure 18. ADC channel support is cross-referenced in the ADC1 chapter.

These figures were redrawn from RM0008 Figure 13 through Figure 18 and intentionally keep a vendor-style black-and-white technical tone. They show the internal one-bit GPIO path selected by MODE/CNF; they are not trainer-board wiring diagrams. Trainer-specific routes are documented in Section 8.

4.1 How to read Figures 2-5

4.2 Configuration bit meaning

4.3 Output speed encoding

5 Package pinout and pin definitions

Real STM32 datasheets do not start pin study from GPIO registers. They first show a package pinout and a pin-definition table. From that table, the reader identifies the package pin, the pad name, the pad type, and the alternate peripheral name. Register lookup then moves to the relevant reference-manual chapter: GPIO, RCC, ADC, TIM, EXTI, or USART.

Figure 6. Reconstructed STM32F103xx performance line LQFP48 pinout used for GPIOA pin reading

Source reconstruction from STM32F103x8/xB DS5319 Rev 20, Figure 8 and Table 5. Reconstructed drawing; no vendor PDF image was pasted.

5.1 Datasheet-style pin definition excerpt

The table below follows the logic of the STM32F103 pin-definition table, but it is intentionally a local reference excerpt rather than the full ST alternate-function list. The Type and I/O level columns answer whether the physical pad can be used as GPIO. The documented-function column only names routes that connect to another HTML chapter in this site. Read the final column in a fixed order: GPIO register inference first, then the owning local chapter, then the current trainer result.

5.2 How PA1 maps to registers

Example: PA1 is a package pad whose type is I/O, so it can be GPIO on the real STM32F103. Because the pin number inside the port is 1, GPIO configuration lives in GPIOA_CRL bits [7:4]. If the selected function is ADC1_IN1, the GPIO chapter only gives the pad-side analog mode; the ADC chapter owns RCC_APB2ENR.ADC1EN, ADC1_CR, and ADC1_DR_CH1.

The same rule applies across the table: PA0..PA7 use GPIOA_CRL, PA8..PA15 use GPIOA_CRH, port output uses ODR/BSRR/BRR, port input uses IDR, locally documented ADC names go to the ADC chapter, timer names go to the TIM chapter, USART names go to the USART chapter, and interrupt use of a GPIO line goes through AFIO/EXTI.

Datasheet reading rule: entries whose type column is I/O and whose I/O level is blank or FT are GPIO-capable package pads before a peripheral route claims the pad. Supply, reset, boot, oscillator-only, and power-reference rows are not treated as ordinary GPIO. Rows not listed in this local excerpt are official-reference behavior or register-latch-only unless another local peripheral chapter owns a trainer route.

Important distinction: on STM32F103-style pin rows, Type = I/O means the silicon pad is a bidirectional GPIO-capable pad. GPIO input-only behavior usually comes from the selected register mode, board wiring, or a trainer route such as PA5 / FAULT_IN, not from the I/O type itself. Rows typed as supply, reset, boot, oscillator-only, or other special-function-only pins should not be tested as ordinary GPIO outputs.

6 Register map and reset values

7 Register descriptions

8 Student register guide and code examples

8.1 Quick first practice path

If a student opens this chapter first, the easiest starting exercise is simple: turn on one visible GPIO output, confirm which register bit moved, then compare that with one input route and one ADC-related route. The chapter should read like a map from pin table to register write to visible proof in the site.

8.2 Input configuration sequence

• Enable the GPIOA peripheral clock first through RCC->APB2ENR.
• Select input mode by writing MODEy = 00; for PA5, this is MODE5 in GPIOA_CRL[23:20].
• Select analog, floating, or pull-up/down behavior through CNFy; for PA6, this is CNF6 in GPIOA_CRL[27:24].
• For pull-up/down input mode, program the corresponding ODRy bit to choose pull direction, such as ODR5 for PA5.
• Read the current logic level through GPIOA_IDR.

8.3 Output configuration sequence

• Enable the GPIOA peripheral clock through RCC->APB2ENR.
• Also enable AFIOEN when the route is used together with EXTI source selection or alternate-function setup guidance from another chapter.
• Select output speed through MODEy; for PA3 / DRV_EN, this is MODE3 in GPIOA_CRL[15:12].
• Select push-pull, open-drain, alternate-function push-pull, or alternate-function open-drain through CNFy; for PA4 / DRV_DIR, this is CNF4 in GPIOA_CRL[19:16].
• Use GPIOA_BSRR for atomic bit control.
• Use GPIOA_ODR if a full latch write is intended.

8.4 Practical notes

• A read of GPIOA_ODR returns the latched output data, not necessarily the external pin level under all conditions.
• A read of GPIOA_IDR returns the sampled input level at the pad.
• Analog mode should be used for ADC-connected pins to disable the digital input path and reduce unnecessary digital switching.
• For PA1 / CURRENT_SENSE, GPIO analog mode is only the pad-side prerequisite. Actual ADC conversion also needs RCC->APB2ENR.ADC1EN and the ADC-side flow described in the ADC chapter.
• PA1 / CURRENT_SENSE is the visible ADC-gated route in the current trainer; configuring it as a GPIO output changes only the GPIO latch, not the rendered current-sense signal.
• PA5 / FAULT_IN and PA6 / HALL_IN remain board-driven inputs in the current trainer even if GPIOA_CRL selects an output mode.
• For interrupt-driven digital inputs, configure the pin as input and use the external interrupt controller separately.
• Alternate-function outputs still require correct GPIO pin mode in CRL/CRH even when the waveform source comes from a timer or communication peripheral. The peripheral clock on the timer or communication block must also be enabled separately.
• In the current trainer, named GPIO outputs stay at 0 V until the matching APB2 clock bit is enabled and the pin mode is set to output.
• If a student configures the wrong path, the UI usually explains the mismatch in plain detail text such as GPIOA clock gated / 0.00 V, Pin mode is not output / 0.00 V, or output writes latch only.
• For first-pass proof, read the chapter with the site views in this order: Register for clock and mode truth, Pin for direction and register source, Graph for the visible trace, and Watch / Access for watched values and register reads/writes.
• The current motor-driver lab named routes are PA1 / CURRENT_SENSE, PA2 / PWM_OUT, PA3 / DRV_EN, PA4 / DRV_DIR, PA5 / FAULT_IN, and PA6 / HALL_IN. UART and PA0 speed feedback are outside this first-review motor lab map.

// Example 1: configure PA3 as general-purpose push-pull output
RCC->APB2ENR |= (1u << 2);   // IOPAEN
GPIOA->CRL &= ~(0xFu << (3 * 4));
GPIOA->CRL |=  (0x2u << (3 * 4)); // MODE3=10 (2 MHz), CNF3=00 (GP push-pull)
GPIOA->BSRR = (1u << 3);          // set PA3
GPIOA->BSRR = (1u << (16 + 3));   // reset PA3

// Example 2: configure PA6 as floating input
GPIOA->CRL &= ~(0xFu << (6 * 4));
GPIOA->CRL |=  (0x4u << (6 * 4));
if (GPIOA->IDR & (1u << 6)) {
    // PA6 input state is HIGH
}

위 예시는 특정 응용회로를 전제로 하지 않는 GPIO 사용 예시입니다. 실제 제품에서는 같은 방식으로 LED, 드라이버 enable, Hall signal, 버튼, 통신 핀 등을 각각의 포트 비트에 매핑해 사용합니다.

Peripheral clock enable에 대한 상세 설명은 별도 문서 RCC Clock Control Datasheet를 참고합니다. The PA1 / CURRENT_SENSE analog flow continues in the separate ADC1 Datasheet as IOPAEN -> ADC1EN -> ADCCLK -> analog mode -> conversion.

8.5 Current trainer GPIO connection map and GPIOB quick routes

Read each GPIO route in this order: pin-definition evidence first, then the RCC gate, then the GPIO configuration field, then the data register, then the visible board or UI signal. A pin is GPIO-capable in the STM32-style document when its package row is an I/O pad and its main reset function is the same port name, such as PA3 or PB0. The PB0/PB1 rows below are included only as a GPIOB quick-route appendix for visible trainer outputs; they do not imply ownership by the GPIOA register block.